1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device with a power-up scheme.
2. Description of the Related Art
In general, a semiconductor device using an external power supply voltage includes a power-up signal generation circuit to ensure a stable operation of an internal circuit. The power-up signal generation circuit activates a power-up signal when an external power supply voltage supplied from an exterior has reached a target voltage level for the stable operation of the internal circuit.
The power-up signal is used as a reset signal for initializing the internal circuit, an enable signal for controlling the operation of the internal circuit, and the like. For example, the power-up signal may be used to enable an internal voltage generation circuit, an e-fuse array, and the like.
Meanwhile, in the semiconductor device, when the internal circuit, enabled in response to the power-up signal, operates using the internal voltage as a source voltage, it may be difficult to ensure the operation stability of the internal circuit. That is, since the internal voltage is also generated in response to the power-up signal, when the internal circuit uses the internal voltage before the internal voltage is stabilized (i.e., reaches a target voltage level), the operation of the internal circuit may become unstable. For example, a fuse read operation is performed in an e-fuse array using the internal voltage through a power-up sequence of the semiconductor device. Since the internal voltage generation circuit for generating the internal voltage is also enabled in the power-up sequence (i.e., based on the power-up signal), the internal voltage may be generated in an unstable state, and thus the programmed data of the e-fuse array may not be normally loaded in the fuse read operation.